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datasheet vs1001 k VS1001K - mpeg audio codec features 2 mpeg audio layer 3 decoder (iso11172-3) 2 supports mpeg 1 & 2, and 2.5 extensions, all their sample rates and bit rates, in mono and stereo 2 supports pcm input 2 supports vbr (variable bitrate) 2 can be used as a slave co-processor 2 operates with single clock 12..13 mhz or 24..26 mhz 2 low-power operation 2 on-chip high-quality stereo dac with no phase error between channels 2 internal op-amp in bga-49 and lqfp-48 packages 2 stereo earphone driver capable of driving a 30 load. 2 separate 2.5 .. 3.6v operating voltages for analog and digital 2 4 kib on-chip ram for user code 2 serial control and data interfaces 2 new functions may be added with software description VS1001K is a single-chip solution for an mpeg layer 3 audio decoder. the chip contains a high- performance low-power dsp processor (vs dsp), working memory, 4 kib program ram and 0.5 kib data ram for user applications, serial con- trol and input data interfaces, and a high-quality oversampling variable-sample-rate stereo dac, fol- lowed by an earphone ampli?er and a ground buffer. VS1001K receives its input bitstream through a serial input bus, which it listens to as a system slave. the input stream is decoded and passed through a analog/digital hybrid volume control to an 18-bit oversampling multi-bit sigma-delta dac. the decoding is controlled via a serial control bus. in addition to the basic decoding, it is possible to add application speci?c features, like dsp effects, to the user ram memory. version 4.14, 2004-02-10 1 vlsi solution y vs_dsp x?ram x?rom y?rom y?ram programrom programram serialdata interface serialcontrol interface stereodac audiooutput dclksdata bsync so si sclk xcs dreq lr vs1001 stereo ear?phone driver x bus y bus i bus scibus sdibus
datasheet vs1001 k contents contents 1 license 7 2 characteristics & speci?cations 7 2.1 analog characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 dac interpolation filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 dac interpolation filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 switching characteristics - clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 switching characteristics - dreq signal . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 switching characteristics - spi interface output . . . . . . . . . . . . . . . . . . . . . . 10 2.11 switching characteristics - boot initialization . . . . . . . . . . . . . . . . . . . . . . . 10 3 packages and pin descriptions 11 3.1 soic-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 bga-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 lqfp-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 example connection diagrams 14 4.1 connection diagram, soic-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 connection diagram, bga-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 connection diagram, lqfp-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 version 4.14, 2004-02-10 2 vlsi solution y
datasheet vs1001 k contents 5 spi buses 17 5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 spi bus pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 serial protocol for serial data interface (sdi) . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 serial protocol for serial command interface (sci) . . . . . . . . . . . . . . . . . . . . 18 5.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4.2 sci read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4.3 sci write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 functional description 21 6.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 data flow of VS1001K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 serial data interface (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 serial control interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5.1 mode (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.5.2 status (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5.3 int fcntlh (-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5.4 clockf (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5.5 decode time (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5.6 audata (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5.7 wram (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5.8 wramaddr (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5.9 hdat0 and hdat1 (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 version 4.14, 2004-02-10 3 vlsi solution y
datasheet vs1001 k contents 6.5.10 aiaddr (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5.11 vol (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5.12 reserved (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5.13 aictrl[x] (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.6 stereo audio dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 operation 29 7.1 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.4 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.5 play/decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6 sanity checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.7 pcm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.8 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.8.1 memory test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.8.2 sci test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.8.3 sine test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 writing software 33 8.1 when to write software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 the processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3 users memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.4 hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.4.1 sci registers, 0x4000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.4.2 serial registers, 0x4100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 version 4.14, 2004-02-10 4 vlsi solution y
datasheet vs1001 k contents 8.4.3 dac registers, 0x4200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.4.4 interrupt registers, 0x4300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.5 system vector tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5.1 audioint, 0x4000..0x4001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5.2 spiint, 0x4002..0x4003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5.3 dataint, 0x4004..0x4005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5.4 usercodec, 0x4008..0x4009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.6 system vector functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.6.1 writeiram(), 0x4010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.6.2 readiram(), 0x4011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.6.3 datawords(), 0x4012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.6.4 getdatabyte(), 0x4013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.6.5 getdatawords(), 0x4014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 vs1001 version changes 38 9.1 changes between vs1001h and production version VS1001K, 2001-08 . . . . . . . . . 38 9.2 changes between vs1001g and vs1001h, 2001-05 . . . . . . . . . . . . . . . . . . . . 38 9.3 changes between vs1001d to vs1001g, 2001-03 . . . . . . . . . . . . . . . . . . . . . 38 10 document version changes 39 10.1 changes between version 4.13 and 4.14 for VS1001K, 2004-02 . . . . . . . . . . . . . 39 10.2 changes between version 4.12 and 4.13 for VS1001K, 2003-11 . . . . . . . . . . . . . 39 10.3 changes between version 4.11 and 4.12 for VS1001K, 2003-10 . . . . . . . . . . . . . 39 10.4 changes between version 4.10 and 4.11 for VS1001K, 2003-09 . . . . . . . . . . . . . 39 10.5 changes between version 4.08 and 4.10 for VS1001K, 2003-07 . . . . . . . . . . . . . 39 10.6 changes between version 4.07 and 4.08 for VS1001K, 2003-03 . . . . . . . . . . . . . 39 version 4.14, 2004-02-10 5 vlsi solution y
datasheet vs1001 k list of figures 11 contact information 40 list of figures 1 pin con?guration, soic-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 pin con?guration, bga-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 pin con?guration, lqfp-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 typical connection diagram using soic-28. . . . . . . . . . . . . . . . . . . . . . . . 14 5 typical connection diagram using bga-49. . . . . . . . . . . . . . . . . . . . . . . . 15 6 typical connection diagram using lqfp-48. . . . . . . . . . . . . . . . . . . . . . . . 16 7 bsync signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 sci word read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 sci word write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 spi timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 data flow of VS1001K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12 built-in bass/treble enhancer frequency response at 44.1 khz. . . . . . . . . . . . . . 24 13 users memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 version 4.14, 2004-02-10 6 vlsi solution y
datasheet vs1001 k 1. license 1 license mpeg layer-3 audio decoding technology licensed from fraunhofer iis and thomson. 2 characteristics & speci?cations unless otherwise noted: avdd=2.9..3.6v, dvdd=2.3..3.6v, ta=-30..+85 c, xtali=24.576mhz, full- scale output sinewave at 1.526 khz, measurement bandwidth 20..20000 hz, analog output load 30 (no ground buffer) or 100 (with ground buffer), bitstream 128 kbits/s, local components as shown in figures 4 and 5. note, that some analog values are in practice better than in these tables if chips are used within a limited temperature range and not too close to lower voltage limits. 2.1 analog characteristics parameter symbol min typ max unit dac resolution 16 bits total harmonic distortion thd 0.1 0.2 % dynamic range (dac unmuted, a-weighted) idr 90 db s/n ratio (full scale signal) snr 70 87 db interchannel isolation 50 75 db interchannel gain mismatch -0.5 0.5 db frequency response -0.1 0.1 db frequency response, avdd = 2.8v -0.3 0.3 db full scale output voltage (peak-to-peak) 1.4 1.8 1 2.0 vpp deviation from linear phase 5 out of band energy -60 db out of band energy with analog filter -90 db analog output load resistance, no ground buffer aolr1 16 30 2 analog output load resistance, ground buffer aolr2 16 100 2 analog output load capacitance 1000 pf 1 3.6 volts can be achieved with +-to-+ wiring for mono difference sound. 2 aolr1/2 may be much lower, but below typical distortion performance may be compromised. version 4.14, 2004-02-10 7 vlsi solution y
datasheet vs1001 k 2. characteristics & specifications 2.2 power consumption parameter symbol min typ max unit power supply rejection 40 db power supply consumption avdd, reset 0.6 5.0 1 a power supply consumption avdd, no load 3.0 4.5 6.0 ma power supply consumption avdd, output loaded at 30 4.0 5.5 40.0 ma power supply consumption avdd, o. @ 30 + gnd-buf. 6.0 7.5 40.0 ma power supply consumption dvdd, reset 3.7 100.0 1 a power supply consumption dvdd 15.0 ma 2.3 dac interpolation filter characteristics parameter symbol min typ max unit passband (to -3db corner) 0 0.459fs hz passband (ripple spec) 0 0.420fs hz passband ripple 0.056 db transition band 0.420fs 0.580fs hz stop band 0.580fs hz stop band rejection 90 db group delay 15/fs s fs is conversion frequency 2.4 dac interpolation filter characteristics parameter symbol min typ max unit -3 db bandwidth 300 khz passband response at 20 khz -0.05 db 2.5 absolute maximum ratings parameter symbol min max unit analog positive supply avdd -0.3 3.6 v digital positive supply dvdd -0.3 3.6 v current at any digital output 50 ma voltage at any digital input dgnd-1.0 dvdd+1.0 v operating temperature -30 +85 c functional operating temperature -40 +95 c storage temperature -65 +150 c version 4.14, 2004-02-10 8 vlsi solution y
datasheet vs1001 k 2. characteristics & specifications 2.6 recommended operating conditions parameter symbol min typ max unit analog and digital ground agnd dgnd 0.0 v positive analog avdd 2.5 1 3.0 3.6 v ambient operating temperature -30 +85 c 1 if avdd is below 2.8 v, distortion performance may be compromised. the following values are to be used when the clock doubler is active: parameter symbol min typ max unit positive digital dvdd 2.3 2.7 3.6 v input clock frequency xtali 12.288 13 mhz internal clock frequency 1 clki 24.576 26 mhz 1 the maximum sample rate that may be decoded with correct speed is clki/512. the following values are to be used when the clock doubler is inactive: parameter symbol min typ max unit positive digital dvdd 2.3 2.7 3.6 v input clock frequency xtali 24.576 26 mhz internal clock frequency 1 clki 24.576 26 mhz 1 the maximum sample rate that may be decoded with correct speed is clki/512. note: with higher than typical voltages, VS1001K may operate with clki upto 30..32 mhz. however, the chips are not quali?ed for this kind of usage. if necessary, vlsi solution oy can qualify chips for higher clock rates for quantity orders. 2.7 digital characteristics parameter symbol min typ max unit high-level input voltage 0.7dvdd v low-level input voltage 0.3dvdd v high-level output voltage at i o = -2.0 ma 0.7dvdd v low-level output voltage at i o = 2.0 ma 0.3dvdd v input leakage current 1.0 1 a version 4.14, 2004-02-10 9 vlsi solution y
datasheet vs1001 k 2. characteristics & specifications 2.8 switching characteristics - clocks parameter symbol min typ max unit master clock frequency 1 xtali 12.288 mhz master clock frequency 2 xtali 24.576 mhz master clock duty cycle 40 50 60 % clock output xtalo xtali mhz 1 clock doubler active. 2 clock doubler inactive. 2.9 switching characteristics - dreq signal parameter symbol min typ max unit data request signal dreq 200 ns 2.10 switching characteristics - spi interface output parameter symbol min typ max unit spi input clock frequency 0.25 clki mhz rise time for so 100 ns 2.11 switching characteristics - boot initialization parameter symbol min max unit reset active time 2 xtali reset inactive to software ready 50000 xtali version 4.14, 2004-02-10 10 vlsi solution y
datasheet vs1001 k 3. packages and pin descriptions 3 packages and pin descriptions 3.1 soic-28 figure 1: pin con?guration, soic-28. pin name pin pin type function dreq 1 do data request, input bus dclk 2 dio serial input data bus clock sdata 3 di serial data input bsync 4 di byte synchronization signal dvdd1 5 pwr digital power supply dgnd1 6 pwr digital ground xtalo 7 clk crystal output xtali 8 clk crystal input dvdd2 9 pwr digital power supply dgnd2 10 pwr digital ground xcs 11 di chip select input (active low) sclk 12 di clock for serial bus si 13 di serial input so 14 do3 serial output test0 15 di reserved for test, connect to dvdd test1 16 do reserved for test, do not connect! test2 17 do reserved for test, do not connect! agnd1 18 pwr analog ground avdd1 19 pwr analog power supply right 20 ao right channel output agnd2 21 pwr analog ground rcap 22 aio ?ltering capacitance for reference avdd2 23 pwr analog power supply left 24 ao left channel output agnd3 25 pwr analog ground xreset 26 di active low asynchronous reset dgnd3 27 pwr digital ground dvdd3 28 pwr digital power supply pin types: type description di digital input, cmos input pad do digital output, cmos input pad dio digital input/output do3 digital output, cmos tri-stated output pad type description ai analog input ao analog output aio analog input/output pwr power supply pin soic-28 package dimensions can be found at http://www.vlsi.?/vs1001/soic28.pdf . version 4.14, 2004-02-10 11 vlsi solution y soic ? 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 xreset dvdddgnd avdd agnd xcs sclk siso sdata dclk bsync dreq xtali xtalo leftright test1 test0 test2 agndavdd dvdddgnd dvdddgnd 15 16 17 18 19 20 21 22 23 27 28 rcapagnd 26 24 25 vs1001
datasheet vs1001 k 3. packages and pin descriptions 3.2 bga-49 figure 2: pin con?guration, bga-49. pin name ball pin type function bsync e3 di byte synchronization signal dvdd1 f3 pwr digital power supply dgnd1 f4 pwr digital ground xtal0 g3 clk crystal output xtali e4 clk crystal input dvdd2 f5 pwr digital power supply dgnd2 f6 pwr digital ground xcs g6 di chip select input (active low) sclk d6 di clock for serial bus si e7 di serial input so d5 do3 serial output test0 c6 di reserved for test, connect to dvdd test1 c7 do reserved for test, do not connect! test2 b6 do reserved for test, do not connect! agnd1 c5 pwr analog ground avdd1 b5 pwr analog power supply right a6 ao right channel output agnd34 b4 pwr analog ground gbgnd a5 pwr analog ground for ground buffer gbuf c4 ao ground buffer gbvdd a4 pwr analog power supply for ground buffer rcap b3 aio ?ltering capacitance for reference avdd45 a3 pwr analog power supply left b2 ao left channel output agnd56 a2 pwr analog ground xreset b1 di active low asynchronous reset dgnd3 d2 pwr digital ground dvdd3 d3 pwr digital power supply dreq e2 do data request, input bus dclk e1 dio serial input data bus clock sdata f2 di serial data input not connected are: a1, a7, b7, c1, c2, c3, d1, d4, d7, e5, e6, f1, f7, g1, g2, g4, g5 and g7. for pin types, see chapter 3.1. bga-49 package dimensions are at http://www.vlsi.?/vs1001/bga49.pdf . version 4.14, 2004-02-10 12 vlsi solution y a bc d e f g 1 2 3 4 5 6 7 top view 0.80 typ 4.807.00 1.10 ref 0.80 typ 1.10 ref 4.807.00 a1 ball pad corner
datasheet vs1001 k 3. packages and pin descriptions 3.3 lqfp-48 figure 3: pin con?guration, lqfp-48. pin name pin pin type function nc 1,2 - xreset 3 di active low asynchronous reset dgnd0 4 pwr digital ground nc 5 - dvdd0 6 pwr digital power supply nc 7 - dreq 8 do data request, input bus dclk 9 di serial input data bus clock sdata 10 di serial data input nc 11,12 - bsync 13 di byte synchronization signal dvdd1 14 pwr digital power supply nc 15 - dgnd1 16 pwr digital ground xtalo 17 ao crystal output xtali 18 ai crystal input dvdd2 19 pwr digital power supply dgnd2 20 pwr digital ground dgnd3 21 pwr digital ground dgnd4 22 pwr digital ground xcs 23 di chip select input (active low) nc 24. . . 27 - sclk 28 di clock for serial bus si 29 di serial input so 30 do3 serial output nc 31 - test0 32 di reserved for test, connect to dvdd test1 33 do reserved for test, do not connect! test2 34 do reserved for test, do not connect! nc 35,36 - agnd0 37 pwr analog ground, low-noise reference avdd0 38 pwr analog power supply right 39 ao right channel output agnd1 40 pwr analog ground gbgnd 41 pwr analog ground gbuf 42 ao ground buffer gbvdd 43 pwr analog power supply rcap 44 aio ?ltering capacitance for reference avdd1 45 pwr analog power supply left 46 ao left channel output agnd2 47 pwr analog ground nc 48 - for pin types, see chapter 3.1. lqfp-48 package dimensions are at http://www.vlsi.?/vs1001/lqfp48.pdf . version 4.14, 2004-02-10 13 vlsi solution y 1 48
datasheet vs1001 k 4. example connection diagrams 4 example connection diagrams 4.1 connection diagram, soic-28 in this connection diagram, a soic-28 -packaged VS1001K is used. figure 4: typical connection diagram using soic-28. ground buffer is not available for the soic-28 package; hence it is not used. version 4.14, 2004-02-10 14 vlsi solution y
datasheet vs1001 k 4. example connection diagrams 4.2 connection diagram, bga-49 in this connection diagram, a bga-49 packaged VS1001K is used. in this picture, ground buffer is active. figure 5: typical connection diagram using bga-49. ground buffer gbuf can be used for common voltage (1.37 v) for earphones. this will eliminate the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1001K may be connected directly to the earphone connector. if gbuf is not used, gbgnd and gbvdd should not be connected. in addition, left and right must be provided with 100 1 f capacitors. version 4.14, 2004-02-10 15 vlsi solution y
datasheet vs1001 k 4. example connection diagrams 4.3 connection diagram, lqfp-48 in this connection diagram, a lqfp-48 packaged VS1001K is used. in this picture, ground buffer is active. figure 6: typical connection diagram using lqfp-48. ground buffer gbuf can be used for common voltage (1.37 v) for earphones. this will eliminate the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1001K may be connected directly to the earphone connector. if gbuf is not used, gbgnd and gbvdd should not be connected. in addition, left and right must be provided with 100 1 f capacitors. version 4.14, 2004-02-10 16 vlsi solution y
datasheet vs1001 k 5. spi buses 5 spi buses 5.1 general the spi bus - that was originally used in some motorola devices - has been used for both VS1001Ks serial data interface sdi (chapters 5.3 and 6.3) and serial control interface sci (chapters 5.4 and 6.4). 5.2 spi bus pin descriptions sdi pin sci pin description - xcs active low chip select input. a high level forces the serial interface into standby mode, ending the current operation. a high level also forces serial output (so) to high impedance state. there is no chip select for sdi, which is always active. dclk sck serial clock input. the serial clock is also used internally as the master clock for the register interface. sck can be gated or continuous. in either case, the ?rst rising clock edge after xcs has gone low marks the ?rst bit to be written (clock 0 in the following ?gures). sdata si serial input. si is sampled on the rising sck edge, if xcs is low. - so serial output. in reads, data is shifted out on the falling sck edge. in writes so is at a high impedance state. 5.3 serial protocol for serial data interface (sdi) the serial data interface can operate in either master or slave mode. in master mode, VS1001K generates the dclk signal, which can be selected to be either 512 or 1024 khz. in slave mode, the dclk signal is generated by an external circuit. the data (sdata signal) can be clocked in at either the rising or falling edge of the dclk. (chapter 6.5). the VS1001K chip assumes its input to be byte-sychronized. i.e. the internal operation of the decoder does not search for byte synchronization of the frames from the data stream, but instead assumes the data to be correctly byte-aligned. the bytes can be transmitted either msb or lsb ?rst, depending of contents of sci register mode (chapter 6.5). figure 7: bsync signal. to ensure correct byte-alignment of the input bitstream, the serial data interface has a bsync signal. version 4.14, 2004-02-10 17 vlsi solution y bsyncsdata dclk d7 d6 d5 d4 d3 d2 d1 d0
datasheet vs1001 k 5. spi buses the ?rst dclk sampling edge (rising or falling, depending on selected polarity), during which the bsync is high, marks the ?rst bit of a byte (lsb, if lsb-?rst order is used, msb, if msb-?rst order is used). if bsync is not used, it must be tied to vcc externally and the master of the input serial interface must always sustain the correct byte-alignment. using bsync is strongly recommended. for more details, look at the application notes for vs10xx. the dreq signal of the data interface is used in slave mode to signal if VS1001Ks fifo is capable of receiving more input data. if dreq is high, VS1001K can take at least 32 bytes of data. when there is less than 32 bytes of free space, dreq is turned low, and the sender should stop transferring new data. because of the 32-byte safety area, the sender may send upto 32 bytes of data at a time without checking the status of dreq, making controlling VS1001K easier for low-speed microcontrollers. note: dreq may turn low or high at any time, even during a byte transmission. thus, dreq should only be used to decide whether to send more bytes. it should not abort a transmission that has already started. 5.4 serial protocol for serial command interface (sci) 5.4.1 general the serial bus protocol for the serial command interface sci (chapter 6.4) consists of an instruction byte, address byte and one 16-bit data word. each read or write operation can read or write a single register. data bits are read at the rising edge, so the user should not update data at the rising edge. the operation is speci?ed by an 8-bit instruction opcode. the supported instructions are read and write. see table below. instruction name opcode operation read 0000 0011 read data write 0000 0010 write data note: after using the serial command interface, it is not allowed to send sci or sdi data for 5 mi- croseconds. 5.4.2 sci read VS1001K registers are read by the following sequence. first, xcs line is pulled low to select the device. then the read opcode (0x3) is transmitted via the si line followed by an 8-bit word address. after the address has been read in, any further data on si is ignored. the 16-bit data corresponding to the received address will be shifted out onto the so line. xcs should be driven high after the data has been shifted out. in that case, the word address will be incremented and data corresponding to the next address will be shifted out. after the last word has been shifted out, xcs should be driven high to end the read sequence. version 4.14, 2004-02-10 18 vlsi solution y
datasheet vs1001 k 5. spi buses word read is shown in figure 8. figure 8: sci word read 5.4.3 sci write VS1001K registers are written by the following sequence. first, xcs line is pulled low to select the device. then the write opcode (0x2) is transmitted via the si line followed by an 8-bit word address. after the word has been shifted in, xcs should be pulled high to end the write sequence. xcs low to high transition must occur after sclk high to low transition corresponding to lsb of the last word. single word write is shown in figure 9. figure 9: sci word write version 4.14, 2004-02-10 19 vlsi solution y 0 0 0 0 0 0 1 1 7 6 5 4 3 2 1 0 15 14 xcssck si instruction (read) address don't care data out so high impedance 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 30 31 1 0 x 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 0 1 2 15 14 xcssck si address data in 0 instruction (write) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 29 30 31 don't care
datasheet vs1001 k 5. spi buses 5.5 spi timing diagram figure 10: spi timing diagram. symbol min max unit txcss 5 ns tsu 10 ns th 42 ns tz 42 ns twl 100 ns twh 100 ns tv 42 ns txcsh 10 ns txcs 2 xtali cycles tdis 1 xtali cycles note: as txcs must be at least 2 clock cycles, the maximum speed for the spi bus is 1/4 of VS1001Ks internal clock speed. for details, see application notes for vs10xx. version 4.14, 2004-02-10 20 xcssck si so 0 1 15 14 16 txcss txcsh twl twh th tsu tv tz tdis txcs vlsi solution y
datasheet vs1001 k 6. functional description 6 functional description 6.1 main features VS1001K is based on a proprietary digital signal processor, vs dsp. it contains all the code and data memory needed for mpeg audio decoding, together with serial interfaces, a multirate stereo audio dac and analog output ampli?ers and ?lters. VS1001K can play all mpeg 1 and 2 layer 3 ?les, as well as so-called mpeg 2.5 layer 3 extension ?les with all sample rates and bitrates. in addition, variable bitrate (vbr) is also supported. with vbr, and depending on the song, near-cd quality can be achieved with approximately 100 kbits/s for stereo music sampled at 44100 hz, whereas old encoders required 128 kbits/s for the same task. as both commercial and free ( http://www.mp3dev.org/ ) high-quality vbr encoders are nowadays widely available, mp3 format is getting better as it is maturing. 6.2 data flow of VS1001K figure 11: data flow of VS1001K. first, mp3 data is input through the sdi bus. after decoding, data may be sent to the bass/treble enhancer depending on sci register modes bit sm bass. then, if sci register aiaddr is non-zero, application code is executed from the address pointed to by aiaddr. for more details, see chapters 6.5.10 and application notes for vs10xx. after the optional user application, the signal is fed to the volume control unit, which also copies the data to the audio fifo. the audio fifo holds the data that is read by the audio interrupt (chapter 8.5.1) and fed to the sample rate converter and dacs. the size of the audio fifo is 512 stereo (2 16-bit) samples the sample rate converter converts all different sample rates to clki/512 and feeds the data to the dac, which in order makes a stereo in-phase signal. this signal is then forwarded to the earphone ampli?er. version 4.14, 2004-02-10 21 bitstreamfifo mp1/2/3decoding bass/trebleenhancer volumecontrol audiofifo s.rate.conv.and dac userapplication r sm_bass = 0sm_bass = 1 a1addr = 0 a1addr != 0 16384 bits 512 stereo samples sdi l vol vlsi solution y
datasheet vs1001 k 6. functional description 6.3 serial data interface (sdi) the serial data interface is meant for transferring compressed mpeg audio data. also several different tests may be activated through sdi as described in chapter 7. 6.4 serial control interface (sci) the serial control interface is compatible with the spi bus speci?cation. data transfers are always 16- bits. the VS1001K is controlled by writing and reading the registers of the interface. the main controls of the control interface are: 2 control of the operation mode 2 uploading user programs 2 access to header data 2 status information 2 access to decoded digital data 2 feeding input data 6.5 sci registers name type addr function mode rw 0 mode control status rw 1 status of VS1001K int fctlh - 2 internal register, never use clockf rw 3 clock freq + doubler decode time r 4 decode time in seconds audata r 5 misc. audio data wram w 6 ram write program wramaddr w 7 base address for ram write hdat0 r 8 read header data hdat1 r 9 read header data aiaddr rw 10 start address of application vol rw 11 volume control reserved - 12 reserved for vs1002 use, dont touch aictrl[x] rw 13+x 2 application control registers x = [0 .. 1] all registers are ?lled with zeros at hardware reset. version 4.14, 2004-02-10 22 vlsi solution y
datasheet vs1001 k 6. functional description 6.5.1 mode (rw) mode is used to control the operation of VS1001K. bit name function value description 0 sm diff differential 0 normal in-phase audio 1 left channel inverted 1 sm ffwd fast forward 0 normal playback 1 fast forward on 2 sm reset soft reset 0 no reset 1 reset 3 sm unused1 set to 0 0 set to 0 4 sm pdown powerdown 0 power on 1 powerdown 5 sm unused2 set to 0 0 set to 0 6 sm unused3 set to 0 0 set to 0 7 sm bass bass/treble enhancer 0 off 1 on 8 sm dact dclk active 0 rising edge 1 falling 9 sm bitord byte order on serial input bus 0 msb ?rst 1 msb last 10 sm ibmode input bus mode 0 slave 1 master 11 sm ibclk input bus clk when VS1001K is master 0 512 khz 1 1024 khz when sm diff is set, the player inverts the left output. for a stereo input, this creates a virtual surround, and for a mono input this effectively creates a differential left/right signal. by setting sm ffwd the player starts to accept sci data at a high speed, and just decodes the audio headers silently without playing any data. this can be used to fast-forward data with safe landing. register decode time is updated during a fast-forward just as normal. by setting sm reset to 1, the player is reset. sm unused1 should always be set to 0. bit sm pdown overrides any other: it turns VS1001K into powerdown mode, where the only opera- tional part is the control bus. (not implemented) sm unused2 and sm unused3 should always be set to 0. bit sm bass turns on the built-in bass and treble enhancer. the frequency response of the enhancer when the sample rate is 44.1 khz is shown in figure 12. for other sample frequencies the response frequence axis must be adjusted accordingly. example: if the sample rate is 48 khz, the 1 khz frequency in the ?gure is actually 1 khz 48 khz / 44.1 khz = 1.09 khz. for details of how much extra processing version 4.14, 2004-02-10 23 vlsi solution y
datasheet vs1001 k 6. functional description power is needed when activating this feature, see application notes for vs10xx. figure 12: built-in bass/treble enhancer frequency response at 44.1 khz. sm dact de?nes the active edge of data clock for sdi. sm bitord de?nes the data bit order inside a byte for sdi. when clear the most signi?cant bit of a byte is sent ?rst and when set, the least signi?cant bit is sent ?rst. bytes are, however, still sent in the default order. this register bit has no effect on the sci bus. sm ibmode sets input bus to master mode. master mode has not been tested, and its use is not recom- mended. sm ibclk sets the bus clock speed when VS1001K is the master. version 4.14, 2004-02-10 24 10 20 50 100 200 500 1k 2k 5k 10k 20k +3+2 +1 0 ?1 ?2 ?3 ampl/db f/hz vlsi solution y
datasheet vs1001 k 6. functional description 6.5.2 status (rw) status contains information on the current status of the VS1001K. bits 1 and 0 are used to control analog output volume: 0 = -0 db, 1 = -6 db, 3 = -12 db. bit 2 is analog powerdown bit. when set to 1, analog is put to powerdown. note: writing to register vol will automatically set the analog output volume, and muting if necessary. thus, the user neednt worry about this register. 6.5.3 int fcntlh (-) int fctlh is not a user-accessible register. 6.5.4 clockf (rw) clockf is used to tell if the input clock xtali is running at something else than 24.576 mhz. xtali is set in 2 khz steps. thus, the formula for calculating the correct value for this register is xt ali= 2000 (xtali is in hz). values may be between 0..32767, although hardware limits the highest allowed speed. also, with lower-than 24.576 mhz speeds all sample rates and bit-stream widths are no longer available. setting the msb of clockf to 1 activates internal clock-doubling. a clock of upto 15 mhz may be doubled depending on the voltage provided to the chip. note: clockf must be set before beginning decoding mp3 data; otherwise the sample rate will not be set correctly. example 1: for a 26 mhz clock the value would be 26000000 = 2000 = 13000 . example 2: for a 13 mhz external clock and using internal clock-doubling for a 26 mhz internal frequency, the value would be 0 x 8000 + (13000000 = 2000) = 39268 . example 3: for a 24.576 mhz clock the value would be either 24576000 = 2000 = 12288 , or just the default value 0 . for this clock frequency, clockf doesnt need to be set at all. 6.5.5 decode time (r) when decoding correct data, current decoded time is shown in this register in full seconds. version 4.14, 2004-02-10 25 vlsi solution y
datasheet vs1001 k 6. functional description 6.5.6 audata (r) when decoding correct data, the current bitrate in kbits/s can be found in bits 8..0 of audata. for a variable bitrate bitstream, the current bitstream width is displayed. bits 12..9 contains an index to the sample rate. the indices are shown in the table below. bits 14..13 are not in use and always set to 0. bit 15 is 0 for mono data and 1 for stereo. bits 12..9 sample rate/hz 0b0000 unknown 0b0001 44100 0b0010 48000 0b0011 32000 0b0100 22050 0b0101 24000 0b0110 16000 0b0111 11025 0b1000 12000 0b1001 8000 6.5.7 wram (w) wram is used to upload application programs to program ram. the start address must be initialized by writing to the wramaddr register prior to the ?rst call of wram. value will be used. as 16 bits of data can be transferred with one wram write, and the program word is 32 bits, two consecutive writes are needed for each program word. the byte order is big-endian (i.e. msbs ?rst). after each full-word write, the internal pointer is autoincremented. 6.5.8 wramaddr (w) wramaddr is used to set the program address for following wram writes. user program space is between addresses 0x4000 .. 0x43ff (with addresses 0x4000 .. 0x401f being reserved by the system), but for writes through the wram mechanism, they are visible at addresses 0x4000 higher. thus, if the programmer wish to write his application to address 0x4167, he should write 0x4167 + 0x4000 = 0x8167 to wramaddr. version 4.14, 2004-02-10 26 vlsi solution y
datasheet vs1001 k 6. functional description 6.5.9 hdat0 and hdat1 (r) bit function value explanation hdat1[15:5] syncword 2047 stream valid hdat1[4:3] id 3 iso 11172-3 1.0 2 mpg 2.0 (1/2-rate) 1 mpg 2.5 (1/4-rate) 0 mpg 2.5 (1/4-rate) hdat1[2:1] layer 3 i 2 ii 1 iii 0 reserved hdat1[0] protect bit 1 no crc 0 crc protected hdat0[15:12] bitrate iso 11172-3 hdat0[11:10] sample rate 3 reserved 2 32/16/8 khz 1 48/24/12 khz 0 44/22/11 khz hdat0[9] pad bit 1 additional slot 0 normal frame hdat0[8] private bit not de?ned hdat0[7:6] mode 3 mono 2 dual channel 1 joint stereo 0 stereo hdat0[5:4] extension iso 11172-3 hdat0[3] copyright 1 copyrighted 0 free hdat0[2] original 1 original 0 copy hdat0[1:0] emphasis 3 ccitt j.17 2 reserved 1 50/15 microsec 0 none when read, hdat0 and hdat1 contain header information that is extracted from mpeg stream being currently being decoded. right after resetting VS1001K, 0 is automatically written to both registers, indicating no data has been found yet. the sample rate ?eld in hdat0 is interpreted as follows: if the id ?eld in hdat1 is 1, the highest sample rate is used. if id is 0, half sample rate is used. for 2 and 3, the lowest sample rate is used. note: the sample rate, stereo/mono and bitrate information can more easily be read from register au- data. version 4.14, 2004-02-10 27 vlsi solution y
datasheet vs1001 k 6. functional description 6.5.10 aiaddr (rw) aiaddr indicates the start address of the application code written earlier through wramaddr and wram registers. if no application code is used, this register should not be initialized, or it should be initialized to zero. for more details, see application notes for vs10xx. 6.5.11 vol (rw) vol is a volume control for the player hardware. for each channel, a value in the range of 0 .. 255 may be de?ned to set its attenuation from the maximum volume level (in 0.5 db steps). the left channel value is then multiplied by 256 and the values are added. thus, maximum volume is 0 and total silence if 65535. example: for a volume of -2.0 db for the left channel and -3.5 db for the right channel: (4*256) + 7 = 1031. note, that at startup volume is set to full volume. resetting the software does not reset the volume setting. note: setting the volume to total silence (255 for both left and right channels), will turn analog power off. this will save power, but also cause a slight snap in the earphones. if you want to turn the volume off but dont want this snap, turn the volume only to 254 for both channels (0xfefe). 6.5.12 reserved (rw) this register has been reserved for future use. 6.5.13 aictrl[x] (rw) aictrl[x] -registers ( x=[0 .. 1] ) can be used to access the users application program. 6.6 stereo audio dac the decoded digital data is transformed into analog format by an 18-bit oversampling multi-bit sigma- delta da-converter. the oversampled output is low-pass ?ltered by an on-chip analog ?lter. the output rate of the da-converter is always 1/4 of the clock rate, or 128 times the highest usable sample rate. for instance for a 24.576 mhz clock, the da-converter operates at 128x48 khz, which is 6.144 mhz. if the input sample rate is other than 48 khz, it is internally converted to 48 khz by the dac. this removes the need for complex pll-based clocking schemes and still allows the use of several sample rates with one ?xed master clock frequency. the outputs can be separately muted by the user. if the output of the decoder is invalid or input data is not received fast enough, analog outputs are automatically muted. the analog outputs have buffers that are capable of driving 30 loads with a maximum of 50nf capacitance. version 4.14, 2004-02-10 28 vlsi solution y
datasheet vs1001 k 7. operation 7 operation 7.1 clocking the VS1001K chip operates typically on a single 24.576 mhz fundamental frequency master clock. this clock can be generated by external circuitry (connected to pin xtali) or by the internal clock chrystal interface (pins xtali and xtalo). this clock is suf?cient to support a high quality audio output for almost all the standard sample rates and bit-rates (see application notes for vs10xx). note: oscillators above 24.576 mhz are usually so-called 3 rd harmonic clocks, which have a fundamen- tal frequency of 1/3 of the nominal clock frequency. with such an oscillator, vs1001 would be running at the base frequency, if working at all. thus, for instance, if you run vs1001 with a 32 mhz 3 rd harmonic clock, you usually end up running the chip at 32 mhz / 3 = 10.67 mhz. 7.2 powerdown in powerdown mode the chip only monitors the control bus. the analog output drivers are turned off and the processor remains in hold-state. 7.3 hardware reset when the xreset -signal is driven low, VS1001K is reset and all the control registers and internal states are set to the initial values. xreset-signal is asynchronous to any external clock. the reset mode doubles as a full-powerdown mode, where both digital and analog parts of VS1001K are in minimum power consumption stage, and where clocks are stopped. also xtalo and xtali are grounded. after a hardware reset (or at power-up), set the basic software registers such as vol for volume (and clockf if the input clock is anything else than 24.576 mhz) before starting decoding. 7.4 software reset between any two mp3 ?les, the decoder software has to be reset. this is done by activating bit 2 in scis mode register (chapter 6.5.1). then wait for at least 2 1 s, then look at dreq. dreq will stay down for at least 6000 clock cycles, which means an approximate 250 1 s delay if VS1001K is run at 24.576 mhz. when dreq goes up, write at least one zero to sdi. after this, you may continue playback as usual. if you want to make sure VS1001K doesnt cut the ending of low-bitrate data streams, it is recommended to feed 2048 zeros to the sdi bus before activating the reset bit (dreq must be respected just as with normal sdi data). this will make sure all frames have been decoded before resetting the chip. version 4.14, 2004-02-10 29 vlsi solution y
datasheet vs1001 k 7. operation 7.5 play/decode this is the normal operation mode of VS1001K. the sdi data is decoded. decoded samples are converted to analog domain by the internal dac, if there are errors in the decoding process, the error ?ags of scis hdat0 and hdat1 are set accordingly. in case there are serious errors in the input data, decoding is still continued, but the analog outputs are muted. when there is no valid input for decoding, VS1001K goes into idle mode (lower power consumption than during decoding) and actively monitors the serial data input for valid data. the data input does not need to be clocked (dclk) when no data is sent. the software needs to be reset between mpeg audio stream ?les. see for the chapter testing to see how it is done. 7.6 sanity checks although VS1001K checks extensively for bad mp3 streams, it may happen that it encounters a bitstream that makes the ?rmwares recovery code fail. this may particularly happen during fast forward and fast backwards operations, where the data where the microcontroller lands the mp3 decoder may not be a valid header. the microcontroller should keep a look at the data speeds VS1001K requires. if data input either stops completely (dreq always inactive) for a whole second, or if VS1001K requires more than 60 kib data in any single second, it is the responsibility of the microcontroller to either reset the software. if that doesnt help, a hardware reset should be issued. 7.7 pcm mode VS1001K can be used as a digital-to-analog converter (dac) by feeding pcm data. a convenient way to use VS1001K as a dac is to load sdi pcm extension for VS1001K software from vlsi solutions home page at http://www.vlsi.?/vs1001/software/ . the sdi pcm extension makes it possible for the user to use sdi to feed 8-bit or 16-bit pcm samples in mono or stereo at any sample rate upto 48 khz (with nominal 24.576 mhz operating frequency). 7.8 testing there are several test modes in VS1001K, which allow the user to perform memory tests, sci bus tests, and several different sine wave tests ranging from 250 hz to 1500 hz. all tests are started in a similar way: vs1001 is hardware reset, and then a test command is sent to the sdi bus. each test is started by sending a 4-byte special command sequence, followed by 4 zeros. the sequences are described below. version 4.14, 2004-02-10 30 vlsi solution y
datasheet vs1001 k 7. operation 7.8.1 memory test memory test mode is initialized with the 8-byte sequence 0x4d 0xea 0x6d 0x54 0 0 0 0. after this command (and its required 4 zeros), wait for 500000 clock cycles. the result can be read from the sci register hdat0, and one bits are interpreted as follows: bit(s) meaning 0 good x rom 1 good y rom (high) 2 good y rom (low) 3 good y ram 4 good x ram 5 good instruction ram (high) 6 good instruction ram (low) 7 unused all tests are non-destructive and interrupts are disabled during testing. thus, no user software or data is harmed by the tests. instruction rom cannot be tested with software. 7.8.2 sci test sci test is initialized with the 8-byte sequence 0x53 0x70 0xee n 0 0 0 0, where n ? 48 is the register number to test. the content of the given register is read and copied to hdat0. if the register to be tested is hdat0, the result is copied to hdat1. example: if n is 48, contents of sci register 0 (mode) is copied to hdat0. version 4.14, 2004-02-10 31 vlsi solution y
datasheet vs1001 k 7. operation 7.8.3 sine test sine test is initialized with the 8-byte sequence: 0x53 0xef 0x6e n 0 0 0 0, where n (48..119) de?nes the sine test to use. if we de?ne f sidx = ( n ? 48) mod 9 and f sin = ( n ? 48) = 9 , the following tables may be used: fsidx fs 0 44100 hz 1 48000 hz 2 32000 hz 3 22050 hz 4 24000 hz 5 16000 hz 6 11025 hz 7 12000 hz 8 8000 hz fsin length of sin 0 32.000 samples 1 16.000 samples 2 10.667 samples 3 8.000 samples 4 6.400 samples 5 5.333 samples 6 4.571 samples 7 4.000 samples example: sine test is called with a test value of 62. 62-48 = 14, fsidx = 5 and fsin = 1. from the tables we get the sample rate 16000 hz, and the sine wave length, which is 16 samples. thus, well get a 1 khz voice. to exit the sine test, send the sequence 0x45 0x78 0x69 0x74 0 0 0 0. note: the sine test signals go through the digital volume control, so it is possible to test channels separately. version 4.14, 2004-02-10 32 vlsi solution y
datasheet vs1001 k 8. writing software 8 writing software 8.1 when to write software user software is required when a user wishes to add some own functionality like dsp effects or tone controls to VS1001K. some tone controls are available from vlsi solution, but if a user wishes to go further than that or use VS1001K in some unexpected way, this is how to do it. however, most of the users of VS1001K dont need to worry about writing their own code, or this chapter. 8.2 the processor core vs dsp is a 16/32-bit dsp processor core that can very well also be used as an all-purpose processor. the vlsi solutions free vskit software package contains all the tools and documentation needed to write, simulate and debug assembly language or extended ansi c programs for the vs dsp processor core. the vskit software package is available on request from vlsi solution. 8.3 users memory map users memory map is shown in figure 13. 8.4 hardware registers all hardware registers are located in x memory. 8.4.1 sci registers, 0x4000 all sci registers described in chapter 6.5 can be found here between 0x4000..0x40ff. 8.4.2 serial registers, 0x4100 ser data (0x4100) contains the last data value read from the data bus. the lsb of ser dreq (0x4101) de?nes the status of the dreq signal. version 4.14, 2004-02-10 33 vlsi solution y
datasheet vs1001 k 8. writing software figure 13: users memory map. 8.4.3 dac registers, 0x4200 dac data should be written at each audio interrupt to dac left (0x4200) and dac right (0x4201) as signed values. int fctll (0x4202) is not a user-serviceable register. 8.4.4 interrupt registers, 0x4300 int enable (0x4300) controls the interrupts. bit 0 switches the dac interrupt on (1) and off (0), bit 1 controls the sci interrupt, and bit 2 controls the data interrupt. it may take upto 6 clock cycles before changing this register has any effect. by writing any value to int glob dis (0x4301) adds one to the interrupt counter and effectively disables all interrupts. it may take upto 6 clock cycles before writing this register has any effect. writing any value to int glob ena (0x4302) subtracts one from the interrupt counter. if the interrupt counter becomes zero, interrupts selected with int enable are restored. an interrupt routine should always write to this register as the last thing it does, because interrupts automatically add one to the interrupt counter, but subtracting it back to its initial value is on the responsibility of the user. it may take upto 6 clock cycles before writing this register has any effect. by reading int counter (0x4303) the user may check if the interrupt counter is correct or not. if the register is not 0, interrupts are disabled. this register may not be written to. version 4.14, 2004-02-10 34 vlsi solution y 00000097 00000097 stack stack instruction (32?bit) y (16?bit) x (16?bit) 40004020 43ff 8000 83ff 40004020 43ff 8000 83ff userspace system vectors 8020 8020 instructionshadow memory msbs instructionshadow memory lsbs hardwareregisters userinstruction space 078007ff 1380 13ff 078007ff 1380 13ff userspace
datasheet vs1001 k 8. writing software 8.5 system vector tags the system vector tags are tags that may be replaced by the user to take control over several decoder functions. 8.5.1 audioint, 0x4000..0x4001 normally contains the following vs dsp assembly code: j dac_int stx mr1,(i6)+1 ; sty i7,(i6) the user may, at will, replace the ?rst instruction with either a j or jmpi command to gain control over the audio interrupt. it is not recommended to change the instruction at 0x4001. 8.5.2 spiint, 0x4002..0x4003 normally contains the following vs dsp assembly code: j spi_int stx mr1,(i6)+1 ; sty i7,(i6) the user may, at will, replace the ?rst address with either a j or jmpi command to gain control over the sci interrupt. it is not recommended to change the instruction at 0x4003. 8.5.3 dataint, 0x4004..0x4005 normally contains the following vs dsp assembly code: j data_int stx mr1,(i6)+1 ; sty i7,(i6) the user may, at will, replace the ?rst address with either a j or jmpi command to gain control over the mp3 data interrupt. it is not recommended to change the instruction at 0x4005. 8.5.4 usercodec, 0x4008..0x4009 normally contains the following vs dsp assembly code: jr nop version 4.14, 2004-02-10 35 vlsi solution y
datasheet vs1001 k 8. writing software if the user wants to take control away from the standard decoder, the ?rst instruction should be replaced with an appropriate jump command to users own code. unless the user is feeding mp3 data at the same time, the system activates the user program in less than 1 ms. after this, the user should steal interrupt vectors from the system, and then insert user programs. 8.6 system vector functions the system vector functions are pointers to some functions that the user may call to help implementing his own applications. 8.6.1 writeiram(), 0x4010 vs dsp c prototype: void writeiram(register i0 u int16 *addr, register a1 u int16 msw, register a0 u int16 lsw); this is the only supported way to write to the user instruction ram. this is because instruction ram cannot be written when program control is in ram. thus, the actual implementation of this function is in rom, and here is simply a tag to that routine. note: instruction ram is shadowed 0x4000 addresses higher in the x and y rams. thus, if you want to write to instruction address 0x4020, addr must be 0x4020 + 0x4000 = 0x8020. 8.6.2 readiram(), 0x4011 vs dsp c prototype: u int32 readiram(register i0 u int16 *addr); this is the only supported way to read from the user instruction ram. this is because instruction ram cannot be read when program control is in ram. thus, the actual implementation of this function is in rom, and here is simply a tag to that routine. a1 contains the msbs and a0 the lsbs of the result. note: instruction ram is shadowed 0x4000 addresses higher in the x and y rams. thus, if you want to read from instruction address 0x4020, addr must be 0x4020 + 0x4000 = 0x8020. version 4.14, 2004-02-10 36 vlsi solution y
datasheet vs1001 k 8. writing software 8.6.3 datawords(), 0x4012 vs dsp c prototype: u int16 datawords(void); if the user has taken over the normal operation of the system by switching the pointer in usercodec to point to his own code, he may read data from the data interface through this and the following two functions. this function returns the number of data words (each containing two bytes of data) that can be read. if there is not enough data available, data acquisition functions getdatabyte() and getdatawords() may not be called! 8.6.4 getdatabyte(), 0x4013 vs dsp c prototype: u int16 getdatabyte(void); reads and returns one data byte from the data interface. before calling this function, always check ?rst that there are at least 1 word waiting with function data- words(). 8.6.5 getdatawords(), 0x4014 vs dsp c prototype: void getdatawords(register i0 y u int16 *d, register a0 u int16 n); read n data byte pairs and copy them in big-endian format (?rst byte to msbs) to d . before calling this function, always check ?rst that there are at least 1+ n words waiting with function datawords(). version 4.14, 2004-02-10 37 vlsi solution y
datasheet vs1001 k 9. vs1001 version changes 9 vs1001 version changes this chapter describes changes between different generations of vs1001. note: VS1001K is the ?nal, production version of vs1001. 9.1 changes between vs1001h and production version VS1001K, 2001-08 2 when the chip is reset with pin xreset, xtalo and xtali are driven to ground. 2 running with normal clock earlier required slightly different clock generation than for clock- doubled (see chapters 4.1 and 4.2). this is no longer the case. 2 lots of new sci register mode bits: sm diff, sm ffwd, sm bass. for details, see chap- ter 6.5.1. 2 default is now to only decode mp3. 2 20..60 mv dac offset corrected. 2 a ?rmware bug made it impossible to decode 320 kbits/s mp3 data. this has been corrected. 2 a hardware bug made it practically impossible to load code to ram. this has been corrected. 9.2 changes between vs1001g and vs1001h, 2001-05 2 analog voltage requirements have been lowered. now full gain can be achieved with a 2.7 v analog input voltage, whereas 3.4 v was needed before. 9.3 changes between vs1001d to vs1001g, 2001-03 2 clock is now adjustable, in vs1001d only 24.576 mhz could be used. 2 clock doubler added. 2 vs1001d played 48 khz instead of 12 or 24 khz, this is corrected. version 4.14, 2004-02-10 38 vlsi solution y
datasheet vs1001 k 10. document version changes 10 document version changes this chapter describes the most important changes to this document. 10.1 changes between version 4.13 and 4.14 for VS1001K, 2004-02 2 new pin names for pins 41 (gbgnd) and 43 (gbvdd) in lqfp-48 pin description, chap- ter 6.5.1. 2 renamed sm byteord to sm bitord, see chapter 3.3. 10.2 changes between version 4.12 and 4.13 for VS1001K, 2003-11 2 changed pin 42 (vcm) to gbuf in chapter 3.3. 2 added example connection diagram for lqfp-48, chapter 4.3. 10.3 changes between version 4.11 and 4.12 for VS1001K, 2003-10 2 in chapter 3.3, test1 and test2 were told to be connected to pin 32 in lqfp-48 packaging, now corrected to pins 33 and 34, respectively. 10.4 changes between version 4.10 and 4.11 for VS1001K, 2003-09 2 minor modi?cations to front page. 2 moved all application notes to a separate document, vs10xx application notes. 10.5 changes between version 4.08 and 4.10 for VS1001K, 2003-07 2 added lqfp-48 packaging, chapter 3.3. 2 removed package ?gure for bga-49 and provided an url instead. 10.6 changes between version 4.07 and 4.08 for VS1001K, 2003-03 2 removed mp1 and mp2 functionality due to ?rmware problems. 2 removed chapter errata. version 4.14, 2004-02-10 39 vlsi solution y
datasheet vs1001 k 11. contact information 11 contact information vlsi solution oy hermiankatu 6-8 c fin-33720 tampere finland fax: +358-3-316 5220 phone: +358-3-316 5230 email: sales@vlsi.? url: http://www.vlsi.?/ note: if you have questions, ?rst see http://www.vlsi.?/vs1001/faq/ . version 4.14, 2004-02-10 40 vlsi solution y

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